Extremely small nonvolatile memory cells are required for very large scale integration density in multimedia applications. The further development of semiconductor technology is enabling increasingly larger storage capacities which, however, are not achieved in the context of conventional fabrication technologies.
DE 100 39 441 A1, which is a counterpart application to U.S. Patent Application No. 2002/024092, describes a memory cell having a trench transistor arranged in a trench formed at a top side of a semiconductor body. An oxide-nitride-oxide layer sequence (ONO layer) is in each case present as storage layer between the gate electrode introduced into the trench and the laterally adjoining source region and the drain region adjoining the latter on the other side. This layer sequence is provided for trapping charge carriers (hot electrons) at source and drain.
DE 101 29 958, which is a counterpart application to U.S. Pat. No. 6,548,861, describes a memory cell arrangement in which a further reduction of the dimensions of the memory cells is achieved in conjunction with an access time kept sufficiently short for writing and reading by virtue of the fact that the bit lines are formed with sufficiently low impedance. For this purpose, separate layers or layer sequences patterned in strip form in accordance with the bit lines are arranged as bit lines on the doped source/drain regions of the individual memory transistors. These layer sequences may comprise doped polysilicon or a metallic layer. In particular, the metallic layer may be a siliconized metal layer which is fabricated by the method known by the designation “salicide” as an abbreviation of self-aligned silicide.
NROM memory cells are described in the publication by B. Eitan et al.,: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters 21, 543 (2000). Owing to the particular material properties, source/drain voltages of 4 to 5 volts are typically necessary during programming and erasing for memory cells of this type. Therefore, the channel lengths of the memory transistor cannot be fabricated significantly below 200 nm. It would be desirable, however, if, despite this channel length of 200 nm, the width of the bit lines could be reduced in such a way as to enable a cell area of less than 5 F2. Also desirable are bit lines with sufficiently low electrical resistance, so that multiple connection of the bit lines at intervals within the memory cell array (bit line strapping) could be dispensed with, no contact holes for the electrical connection of the bit lines would have to be fabricated between the word lines and the area required between the bit lines could thereby be reduced.